Clock Gating for Dynamic Power Reduction in Synchronous Circuits

In this paper clock gating technique is presented for low power VLSI (very large scale integration) circuit design. Clock in digital circuits is used for synchronization of various components. Clock power is a major source of dynamic power consumed in synchronous circuits. Clock-gating is a well-known technique to reduce clock power. In clock gating clock to an idle block is disabled. Thus significant amount of power consumption is reduced by employing clock gating. In this paper a 4-bit synchronous counter is designed using clock gating. Simulation is performed on Xilinx ISE design tool. Experimental result shows that the clock gating technique significantly improves total dynamic power consumption. It is observed that approximately 11% of dynamic power is saved. Keywords—Gated clock, low power design, synchronous counter.